1. Which of the following flip-flop is free from race-around problem ?
Correct : D. master- slave jk flip-flop
2. If the input J is connected through K input of J-K, then flip-flop will behave as a
Correct : A. d type flip-flop
3. If a clock with time period 'T' is used with n stage shift register, then output of final stage will be delayed by
Correct : B. (n-1)t sec
4. Register is a
Correct : C. temporary storage unit within the cpu having dedicated or general purpose use
5. The number of flip-flops required in a decade counter is
Correct : B. 4
6. If in a shift resistor Q0 is fed back to input the resulting counter is
Correct : C. twisted ring with 2n : 1 scale
7. A 8-bit serial in / parallel out shift register contains the value “8”, clock signal(s) will be required to shift the value completely out of the register.
Correct : D. 8
8. In a sequential circuit the next state is determined by and
Correct : D. input and clock signal applied
9. The divide-by-60 counter in digital clock is implemented by using two cascading counters:
Correct : A. mod-6, mod-10
10. In NOR gate based S-R latch if both S and R inputs are set to logic 0, the previous output state is maintained.
Correct : A. true
11. The minimum time for which the input signal has to be maintained at the input of flip-flop is called of the flip-flop.
Correct : B. hold time
12. 74HC163 has two enable input pins which are and
Correct : A. enp, ent
13. to change in one input variable
Correct : B. condition
14. The input overrides the input
Correct : A. asynchronous
, synchronous
15. A decade counter is .
Correct : D. mod-10 counter
16. In asynchronous transmission when the transmission line is idle,
Correct : B. it is set to logic high
17. A Nibble consists of bits
Correct : B. 4
18. The output of this circuit is always .
Correct : C. a
19. Excess-8 code assigns to “-8”
Correct : D. 0
20. The voltage gain of the Inverting Amplifier is given by the relation
Correct : A. vout / vin = - rf / ri
21. LUT is acronym for
Correct : A. look up table
22. The three fundamental gates are
Correct : D. not, or, and
23. Stack is an acronym for
Correct : B. lifo
memory
24. is one of the examples of synchronous inputs.
Correct : A. j-k input
25. occurs when the same clock signal arrives at different times at different clock inputs due to
propagation delay
Correct : B. clock skew
26. Consider an up/down counter that counts between 0 and 15, if external input(X) is “0” the counter counts upward (0000 to 1111) and if external input (X) is “1” the counter counts downward (1111 to 0000), now suppose that the present state is “1100” and X=1, the next state of the counter will be
Correct : C. 1011
27. In a state diagram, the transition from a current state to the next state is determined by
Correct : A. current state and the inputs
28. is used to simplify the circuit that determines the next state.
Correct : D. state assignmen t
29. Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100. What
will be the 4-bit pattern after the second clock pulse? (Right-most bit first.)
Correct : C. 0
30. The diagram given below represents
Correct : D. sum of product form
31. The operation of J-K flip-flop is similar to that of the SR flip-flop except that the J-K flip-flop
Correct : A. doesn’t have an invalid state
32. A multiplexer with a register circuit converts
Correct : B. parallel data to serial
33. A GAL is essentially a .
Correct : D. reprogra mmable pal
34. in , all the columns in the same row are either read or written.
Correct : C. fast mode page access
35. How many flip-flops are required to produce a divide-by-32 device?
Correct : B. 5
36. A reduced state table has 18 rows. The minimum number of flip flops needed to implement the sequential machine is
Correct : C. 5
37. Advantage of synchronous sequential circuits over asynchronous ones is
Correct : A. faster operation
38. The characteristic equation of a JK flip flop is
Correct : B. qn+1=j.q’n+ k’.qn
39. WHEN BOTH THE INPUTS OF EDGE-TRIGGERED J-K FLOP-FLOP ARE SET TO LOGIC ZERO -------
Correct : D. the output of flip- flop remains unchang ed
40. In Q output of the last flip-flop of the shift register is connected to the data input of the first
flip-flop of the shift register.
Correct : D. ring counter
41. 5-BIT JOHNSON COUNTER SEQUENCES THROUGH STATES
Correct : B. 10
42. A 8-bit serial in / parallel out shift register contains the value “8”, clock signal(s) will be required to shift
the value completely out of the register.
Correct : D. 8
43. AT T0 THE VALUE STORED IN A 4-BIT LEFT SHIFT WAS “1”. WHAT WILL BE THE VALUE OF
REGISTER AFTER THREE CLOCK PULSES?
Correct : D. 8
44. The alternate solution for a multiplexer and a register circuit is
Correct : A. parallel in / serial out shift register
45. A multiplexer with a register circuit converts
Correct : B. parallel data to serial
46. A synchronous decade counter will have flip-flops
Correct : B. 4
47. In outputs depend only on the current state.
Correct : B. moore machine
48. Given the state diagram of an up/down counter, we can find
Correct : A. the next state of a given present state
49. THE HOURS COUNTER IS IMPLEMENTED USING
Correct : D. a single decade counter and a flip-flop
50. The design and implementation of synchronous counters start from
Correct : D. state diagram
51. THE GLITCHES DUE TO RACE CONDITION CAN BE AVOIDED BY USING A
Correct : D. negative
-edge triggere d flip- flops
52. A positive edge-triggered flip-flop changes its state when
Correct : A. low-to-high transition of clock
53. Flip flops are also called
Correct : C. bi-stable multivibrator s
54. A FIELD-PROGRAMMABLE LOGIC ARRAY CAN BE PROGRAMMED BY THE USER AND NOT BY
THE MANUFACTURER.
Correct : A. true
55. THE FOUR OUTPUTS OF TWO 4-INPUT MULTIPLEXERS, CONNECTED TO FORM A 16-INPUT
MULTIPLEXER, ARE CONNECTED TOGETHER THROUGH A 4-INPUT
GATE
Correct : B. or
56. A particular half adder has
Correct : B. 2 inputs
and 2 output
57. A full-adder has a Cin = 0. What are the sum (<PRIVATE "TYPE=PICT;ALT=sigma"> ) and the carry (Cout)
when A = 1 and B = 1?
Correct : B. = 0, cout = 1
58. The sequence of states that are implemented by a n-bit Johnson counter is
Correct : B. 2n (n multiplied by 2)
59. A GAL is essentially a .
Correct : D. reprogra mmable pal
60. The alternate solution for a demultiplexer-register combination circuit is
Correct : B. serial in / parallel out shift register
61. A transparent mode means
Correct : A. the changes in the data at the inputs of the latch are seen at the output
62. occurs when the same clock signal arrives at different times at different clock inputs due to
propagation delay.
Correct : B. clock skew
63. is one of the examples of asynchronous inputs.
Correct : D. clear input (clr)
64. Bi-stable devices remain in either of their states unless the inputs force the device to switch its state
Correct : D. two
65. RCO Stands for
Correct : D. ripple clock output
66. A positive edge-triggered flip-flop changes its state when
Correct : A. low-to-high transition of clock
67. The low to high or high to low transition of the clock is considered to be a(n)
Correct : B. edge
68. In asynchronous digital systems all the circuits change their state with respect to a common clock
Correct : B. false
69. If the S and R inputs of the gated S-R latch are connected together using a gate then there is only a
single input to the latch. The input is represented by D instead of S or R (A gated D-Latch)
Correct : C. not
70. If S=1 and R=0, then Q(t+1) = for positive edge triggered flip-flop
Correct : B. 1
71. 3-to-8 decoder can be used to implement Standard SOP and POS Boolean expressions
Correct : A. true
72. The Encoder is used as a keypad encoder.
Correct : D. decimal- to-bcd priority
73. The simplest and most commonly used Decoders are the Decoders
Correct : A. n to 2n
74. A Karnaugh map is similar to a truth table because it presents all the possible values of input variables and the
resulting output of each value.
Correct : A. true
75. The decimal “17” in BCD will be represented as 10001(right opt is not given)
Correct : C. 10111
76. Q2 :=Q1 OR X OR Q3
The above ABEL expression will be
Correct : B. q2:= q1 # x
# q3
77. Above is the circuit diagram of
Correct : A. asynchronous up-counter
78. The high density FLASH memory cell is implemented using
Correct : A. 1 floating-gate mos transistor
79. A bidirectional 4-bit shift register is storing the nibble 1110. Its input is LOW. The nibble 0111 is
waiting to be entered on the serial data-input line. After two clock pulses, the shift register is storing .
Correct : D. 1001
80. At T0 the value stored in a 4-bit left shift was “1”. What will be the value of register after three clock pulses?
Correct : D. 8
81. A multiplexer with a register circuit converts
Correct : B. parallel data to serial
82. In outputs depend only on the combination of current state and inputs
Correct : A. mealy machine
83. The input overrides the input
Correct : A. asynchronous, synchronous
84. For a gated D-Latch if EN=1 and D=1 then Q(t+1) =
Correct : B. 1
85. If S=1 and R=1, then Q(t+1) = for negative edge triggered flip- flop
Correct : C. invalid
86. The sequence of states that are implemented by a n-bit Johnson counter is
Correct : B. 2n
87. The alternate solution for a multiplexer and a register circuit is
Correct : A. parallel in / serial out shift register
88. THE GLITCHES DUE TO RACE CONDITION CAN BE AVOIDED BY USING A
Correct : D. negative
-edge triggere d flip- flops
89. Flip flops are also called
Correct : C. bi-stable multivibrator s
90. A transparent mode means
Correct : A. the changes in the data at the inputs of the latch are seen at the output
91. Given the state diagram of an up/down counter, we can find
Correct : A. the next state of a given present state
92. In Q output of the last flip-flop of the shift register is connected to the data input of the first
flip-flop of the shift register.
Correct : D. ring counter
93. status.
Correct : C. 8
94. We have a digital circuit. Different parts of circuit operate at different clock frequencies (4MHZ, 2MHZ
and 1MHZ), but we have a single clock source having a fix clock frequency (4MHZ), we can get help by
Correct : C. j-k flip-flop
95. If S=1 and R=1, then Q(t+1) = for negative edge triggered flip- flop
Correct : C. invalid
96. WHEN BOTH THE INPUTS OF EDGE-TRIGGERED J-K FLOP-FLOP ARE SET TO LOGIC ZERO
Correct : C. q=1 and q’=0
97. If an S-R latch has a 1 on the S input and a 0 on the R input and then the S input goes to 0, the latch will
be
Correct : A. set
98. For a positive edge-triggered J-K flip-flop with both J and K HIGH, the outputs will if the clock goes HIGH.
Correct : A. toggle
99. What is the difference between a D latch and a D flip-flop?
Correct : D. the d flip- flop has a clock input.
100. A frequency counter
Correct : B. counts no. of clock pulses in 1 second