Quiznetik
Digital Logic Circuits (DLC) | Set 2
1. A basic S-R flip-flop can be constructed by cross-coupling of which basic logic gates?
A. and or or gates
B. xor or xnor gates
C. nor or nand gates
D. and or nor gates
Correct : C. nor or nand gates
2. The logic circuits whose outputs at any instant of time depends only on the present input but also on the past outputs are called
A. combinational circuits
B. sequential circuits
C. latches
D. flip-flops
Correct : B. sequential circuits
3. Whose operations are more faster among the following?
A. combinational circuits
B. sequential circuits
C. latches
D. flip-flops
Correct : A. combinational circuits
4. How many types of sequential circuits are?
A. 2
B. 3
C. 4
D. 5
Correct : A. 2
5. The sequential circuit is also called
A. flip-flop
B. latch
C. strobe
D. adder
Correct : B. latch
6. The basic latch consists of
A. two inverters
B. two comparators
C. two amplifiers
D. two adders
Correct : A. two inverters
7. In S-R flip-flop, if Q = 0 the output is said to be
A. set
B. reset
C. previous state
D. current state
Correct : B. reset
8. The output of latches will remain in set/reset untill
A. the trigger pulse is given to change the state
B. any pulse given to go into previous state
C. they don’t get any pulse more
D. the pulse is edge-triggered
Correct : A. the trigger pulse is given to change the state
9. What is a trigger pulse?
A. a pulse that starts a cycle of operation
B. a pulse that reverses the cycle of operation
C. a pulse that prevents a cycle of operation
D. a pulse that enhances a cycle of operation
Correct : A. a pulse that starts a cycle of operation
10. A latch is an example of a
A. monostable multivibrator
B. astable multivibrator
C. bistable multivibrator
D. 555 timer
Correct : C. bistable multivibrator
11. Latch is a device with
A. one stable state
B. two stable state
C. three stable state
D. infinite stable states
Correct : B. two stable state
12. Why latches are called a memory devices?
A. it has capability to stare 8 bits of data
B. it has internal memory of 4 bit
C. it can store one bit of data
D. it can store infinite amount of data
Correct : C. it can store one bit of data
13. Two stable states of latches are
A. astable & monostable
B. low input & high output
C. high output & low output
D. low output & high input
Correct : C. high output & low output
14. How many types of latches are __
A. 4
B. 3
C. 2
D. 5
Correct : A. 4
15. The full form of SR is
A. system rated
B. set reset
C. set ready
D. set rated
Correct : B. set reset
16. The SR latch consists of
A. 1 input
B. 2 inputs
C. 3 inputs
D. 4 inputs
Correct : B. 2 inputs
17. The outputs of SR latch are
A. x and y
B. a and b
C. s and r
D. q and q’
Correct : D. q and q’
18. The first step of analysis procedure of SR latch is to
A. label inputs
B. label outputs
C. label states
D. label tables
Correct : B. label outputs
19. The inputs of SR latch are
A. x and y
B. a and b
C. s and r
D. j and k
Correct : C. s and r
20. When a high is applied to the Set line of an SR latch, then
A. q output goes high
B. q’ output goes high
C. q output goes low
D. both q and q’ go high
Correct : A. q output goes high
21. When both inputs of SR latches are low, the latch
A. q output goes high
B. q’ output goes high
C. it remains in its previously set or reset state
D. it goes to its next set or reset state
Correct : C. it remains in its previously set or reset state
22. When both inputs of SR latches are high, the latch goes
A. unstable
B. stable
C. metastable
D. bistable
Correct : C. metastable
23. The full form of MOS is
A. metal oxide semiconductor
B. metal oxygen semiconductor
C. metallic oxide semiconductor
D. metallic oxygen semiconductor
Correct : A. metal oxide semiconductor
24. What are the types of MOSFET devices available?
A. p-type enhancement type mosfet
B. n-type enhancement type mosfet
C. depletion type mosfet
D. all of the mentioned
Correct : D. all of the mentioned
25. Which insulating layer used in the fabrication of MOSFET?
A. aluminium oxide
B. silicon nitride
C. silicon dioxide
D. aluminium nitrate
Correct : C. silicon dioxide
26. A technique used to reduce the magnitude of threshold voltage of MOSFET is the
A. use of complementary mosfet
B. use of silicon nitride
C. using thin film technology
D. increasing potential of the channel
Correct : B. use of silicon nitride
27. What is used to higher the speed of operation in MOSFET fabrication?
A. ceramic gate
B. silicon dioxide
C. silicon nitride
D. poly silicon gate
Correct : D. poly silicon gate
28. Why MOSFET is preferred over BJT in IC components?
A. mosfet has low packing density
B. mosfet has medium packing density
C. mosfet has high packing density
D. mosfet has no packing density
Correct : A. mosfet has low packing density
29. Critical defects per unit chip area is for a MOS transistor.
A. high
B. low
C. neutral
D. very high
Correct : B. low
30. MOS is being used in
A. lsi
B. vlsi
C. msi
D. both lsi and vlsi
Correct : D. both lsi and vlsi
31. The D flip-flop has input.
A. 1
B. 2
C. 3
D. 4
Correct : A. 1
32. The D flip-flop has output/outputs.
A. 2
B. 3
C. 4
D. 1
Correct : A. 2
33. A D flip-flop can be constructed from an _ flip-flop.
A. s-r
B. j-k
C. t
D. s-k
Correct : A. s-r
34. In D flip-flop, if clock input is HIGH & D=1, then output is
A. 0
B. 1
C. forbidden
D. toggle
Correct : A. 0
35. Which of the following is correct for a gated D flip-flop?
A. the output toggles if one of the inputs is held high
B. only one of the inputs can be high at a time
C. the output complement follows the input when enabled
D. q output follows the input d when the enable is high
Correct : D. q output follows the input d when the enable is high
36. With regard to a D latch
A. the q output follows the d input when en is low
B. the q output is opposite the d input when en is low
C. the q output follows the d input when en is high
D. the q output is high regardless of en’s input state
Correct : C. the q output follows the d input when en is high
37. Which of the following is correct for a D latch?
A. the output toggles if one of the inputs is held high
B. q output follows the input d when the enable is high
C. only one of the inputs can be high at a time
D. the output complement follows the input when enabled
Correct : B. q output follows the input d when the enable is high
38. Which of the following describes the operation of a positive edge-triggered D flip-flop?
A. if both inputs are high, the output will toggle
B. the output will follow the input on the leading edge of the clock
C. when both inputs are low, an invalid state exists
D. the input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock
Correct : B. the output will follow the input on the leading edge of the clock
39. A positive edge-triggered D flip-flop will store a 1 when
A. the d input is high and the clock transitions from high to low
B. the d input is high and the clock transitions from low to high
C. the d input is high and the clock is low
D. the d input is high and the clock is high
Correct : B. the d input is high and the clock transitions from low to high
40. Why do the D flip-flops receive its designation or nomenclature as ‘Data Flip-flops’?
A. due to its capability to receive data from flip-flop
B. due to its capability to store data in flip-flop
C. due to its capability to transfer the data into flip-flop
D. due to erasing the data from the flip-flop
Correct : C. due to its capability to transfer the data into flip-flop
41. The characteristic equation of D-flip-flop implies that
A. the next state is dependent on previous state
B. the next state is dependent on present state
C. the next state is independent of previous state
D. the next state is independent of present state
Correct : D. the next state is independent of present state
42. The asynchronous input can be used to set the flip-flop to the
A. 1 state
B. 0 state
C. either 1 or 0 state
D. forbidden state
Correct : C. either 1 or 0 state
43. Input clock of RS flip-flop is given to
A. input
B. pulser
C. output
D. master slave flip-flop
Correct : B. pulser
44. D flip-flop is a circuit having
A. 2 nand gates
B. 3 nand gates
C. 4 nand gates
D. 5 nand gates
Correct : C. 4 nand gates
45. At the end of the clock pulse the value of output Q is uncertain. The situation is referred to as?
A. conversion condition
B. race around condition
C. lock out state
D. forbidden state
Correct : B. race around condition
46. Master slave flip flop is also referred to as?
A. level triggered flip flop
B. pulse triggered flip flop
C. edge triggered flip flop
D. edge-level triggered flip flop
Correct : B. pulse triggered flip flop
47. In a positive edge triggered JK flip flop, a low J and low K produces?
A. high state
B. low state
C. toggle state
D. no change state
Correct : D. no change state
48. If one wants to design a binary counter, the preferred type of flip-flop is
A. d type
B. s-r type
C. latch
D. j-k type
Correct : D. j-k type
49. S-R type flip-flop can be converted into D type flip-flop if S is connected to R through
A. or gate
B. and gate
C. inverter
D. full adder
Correct : C. inverter
50. Which of the following flip-flops is free from the race around the problem?
A. t flip-flop
B. sr flip-flop
C. master-slave flip-flop
D. d flip-flop
Correct : A. t flip-flop
51. Which of the following is the Universal Flip-flop?
A. s-r flip-flop
B. j-k flip-flop
C. master slave flip-flop
D. d flip-flop
Correct : B. j-k flip-flop
52. How many types of triggering takes place in a flip flops?
A. 3
B. 2
C. 4
D. 5
Correct : A. 3
53. The term synchronous means _
A. the output changes state only when any of the input is triggered
B. the output changes state only when the clock input is triggered
C. the output changes state only when the input is reversed
D. the output changes state only when the input follows it
Correct : B. the output changes state only when the clock input is triggered
54. The S-R, J-K and D inputs are called
A. asynchronous inputs
B. synchronous inputs
C. bidirectional inputs
D. unidirectional inputs
Correct : B. synchronous inputs
55. The characteristic of J-K flip-flop is similar to
A. s-r flip-flop
B. d flip-flop
C. t flip-flop
D. gated t flip-flop
Correct : A. s-r flip-flop
56. A J-K flip-flop can be obtained from the clocked S-R flip-flop by augmenting
A. two and gates
B. two nand gates
C. two not gates
D. two or gates
Correct : A. two and gates
57. What is the significance of the J and K terminals on the J-K flip-flop?
A. there is no known significance in their designations
B. the j represents “jump,” which is how the q output reacts whenever the clock goes high and the j input is also high
C. the letters were chosen in honour of jack kilby, the inventory of the integrated circuit
D. all of the other letters of the alphabet are already in use
Correct : C. the letters were chosen in honour of jack kilby, the inventory of the integrated circuit
58. 48 MHz.
A. 10.24 khz
B. 5 khz
C. 30.24 khz
D. 15 khz
Correct : B. 5 khz
59. How many flip-flops are in the 7475 IC?
A. 2
B. 1
C. 4
D. 8
Correct : C. 4
60. In parts of the processor, adders are used to calculate
A. addresses
B. table indices
C. increment and decrement operators
D. all of the mentioned
Correct : D. all of the mentioned
61. Total number of inputs in a half adder is
A. 2
B. 3
C. 4
D. 1
Correct : A. 2
62. In which operation carry is obtained?
A. subtraction
B. addition
C. multiplication
D. both addition and subtraction
Correct : B. addition
63. If A and B are the inputs of a half adder, the sum is given by
A. a and b
B. a or b
C. a xor b
D. a ex-nor b
Correct : C. a xor b
64. If A and B are the inputs of a half adder, the carry is given by
A. a and b
B. a or b
C. a xor b
D. a ex-nor b
Correct : A. a and b
65. Half-adders have a major limitation in that they cannot
A. accept a carry bit from a present stage
B. accept a carry bit from a next stage
C. accept a carry bit from a previous stage
D. accept a carry bit from the following stages
Correct : C. accept a carry bit from a previous stage
66. The difference between half adder and full adder is
A. half adder has two inputs while full adder has four inputs
B. half adder has one output while full adder has two outputs
C. half adder has two inputs while full adder has three inputs
D. all of the mentioned
Correct : C. half adder has two inputs while full adder has three inputs
67. If A, B and C are the inputs of a full adder then the sum is given by
A. a and b and c
B. a or b and c
C. a xor b xor c
D. a or b or c
Correct : C. a xor b xor c
68. If A, B and C are the inputs of a full adder then the carry is given by
A. a and b or (a or b) and c
B. a or b or (a and b) c
C. (a and b) or (a and b)c
D. a xor b xor (a xor b) and c
Correct : A. a and b or (a or b) and c
69. Half subtractor is used to perform subtraction of
A. 2 bits
B. 3 bits
C. 4 bits
D. 5 bits
Correct : A. 2 bits
70. For subtracting 1 from 0, we use to take a from neighbouring bits.
A. carry
B. borrow
C. input
D. output
Correct : B. borrow
71. How many outputs are required for the implementation of a subtractor?
A. 1
B. 2
C. 3
D. 4
Correct : B. 2
72. Let the input of a subtractor is A and B then what the output will be if A = B?
A. 0
B. 1
C. a
D. b
Correct : A. 0
73. Let A and B is the input of a subtractor then the output will be
A. a xor b
B. a and b
C. a or b
D. a exnor b
Correct : A. a xor b
74. Let A and B is the input of a subtractor then the borrow will be
A. a and b’
B. a’ and b
C. a or b
D. a and b
Correct : B. a’ and b
75. What does minuend and subtrahend denotes in a subtractor?
A. their corresponding bits of input
B. its outputs
C. its inputs
D. borrow bits
Correct : C. its inputs
76. Full subtractor is used to perform subtraction of
A. 2 bits
B. 3 bits
C. 4 bits
D. 8 bits
Correct : B. 3 bits
77. The full subtractor can be implemented using
A. two xor and an or gates
B. two half subtractors and an or gate
C. two multiplexers and an and gate
D. two comparators and an and gate
Correct : B. two half subtractors and an or gate
78. The output of a subtractor is given by (if A, B and X are the inputs).
A. a and b xor x
B. a xor b xor x
C. a or b nor x
D. a nor b xor x
Correct : B. a xor b xor x
79. The output of a full subtractor is same as
A. half adder
B. full adder
C. half subtractor
D. decoder
Correct : B. full adder
80. A register is defined as
A. the group of latches for storing one bit of information
B. the group of latches for storing n-bit of information
C. the group of flip-flops suitable for storing one bit of information
D. the group of flip-flops suitable for storing binary information
Correct : D. the group of flip-flops suitable for storing binary information
81. The register is a type of
A. sequential circuit
B. combinational circuit
C. cpu
D. latches
Correct : A. sequential circuit
82. How many types of registers are?
A. 2
B. 3
C. 4
D. 5
Correct : C. 4
83. The main difference between a register and a counter is
A. a register has no specific sequence of states
B. a counter has no specific sequence of states
C. a register has capability to store one bit of information but counter has n-bit
D. a register counts data
Correct : A. a register has no specific sequence of states
84. In D register, ‘D’ stands for
A. delay
B. decrement
C. data
D. decay
Correct : C. data
85. Registers capable of shifting in one direction is
A. universal shift register
B. unidirectional shift register
C. unipolar shift register
D. unique shift register
Correct : B. unidirectional shift register
86. A register that is used to store binary information is called
A. data register
B. binary register
C. shift register
D. d – register
Correct : B. binary register
87. A shift register is defined as
A. the register capable of shifting information to another register
B. the register capable of shifting information either to the right or to the left
C. the register capable of shifting information to the right only
D. the register capable of shifting information to the left only
Correct : B. the register capable of shifting information either to the right or to the left
88. How many methods of shifting of data are available?
A. 2
B. 3
C. 4
D. 5
Correct : A. 2
89. In serial shifting method, data shifting occurs
A. one bit at a time
B. simultaneously
C. two bit at a time
D. four bit at a time
Correct : A. one bit at a time
90. What is a recirculating register?
A. serial out connected to serial in
B. all q outputs connected together
C. a register that can be used over again
D. parallel out connected to parallel in
Correct : A. serial out connected to serial in
91. When is it important to use a three-state buffer?
A. when two or more outputs are connected to the same input
B. when all outputs are normally high
C. when all outputs are normally low
D. when two or more outputs are connected to two or more inputs
Correct : A. when two or more outputs are connected to the same input
92. After two clock pulses, the register contains
A. 10111000
B. 10110111
C. 11110000
D. 11111100
Correct : D. 11111100
93. How much storage capacity does each stage in a shift register represent?
A. one bit
B. two bits
C. four bits
D. eight bits
Correct : A. one bit
94. The decimal number system represents the decimal number in the form of
A. hexadecimal
B. binary coded
C. octal
D. decimal
Correct : B. binary coded
95. 29 input circuit will have total of
A. 32 entries
B. 128 entries
C. 256 entries
D. 512 entries
Correct : D. 512 entries
96. BCD adder can be constructed with 3 IC packages each of
A. 2 bits
B. 3 bits
C. 4 bits
D. 5 bits
Correct : C. 4 bits
97. The output sum of two decimal digits can be represented in
A. gray code
B. excess-3
C. bcd
D. hexadecimal
Correct : C. bcd
98. The addition of two decimal digits in BCD can be done through
A. bcd adder
B. full adder
C. ripple carry adder
D. carry look ahead
Correct : A. bcd adder
99. 3 bits full adder contains
A. 3 combinational inputs
B. 4 combinational inputs
C. 6 combinational inputs
D. 8 combinational inputs
Correct : D. 8 combinational inputs
100. The simplified expression of full adder carry is
A. c = xy+xz+yz
B. c = xy+xz
C. c = xy+yz
D. c = x+y+z
Correct : A. c = xy+xz+yz