1. The memory which is used to store the copy of data or instructions stored in larger memories, inside the CPU is called
Correct : A. level 1 cache
2. The larger memory placed between the primary cache and the memory is called
Correct : B. level 2 cache
3. The next level of memory hierarchy after the L2 cache is
Correct : D. register
4. The last on the hierarchy scale of memory devices is
Correct : B. secondary memory
5. In the memory hierarchy, as the speed of operation increases the memory size also increases.
Correct : B. false
6. If we use the flash drives instead of the harddisks, then the secondary storage can go above primary memory in the hierarchy.
Correct : B. false
7. The reason for the implementation of the cache memory is
Correct : B. the difference in speeds of operation of the processor and memory
8. The effectiveness of the cache memory is based on the property of
Correct : A. locality of reference
9. The temporal aspect of the locality of reference means
Correct : C. that the recently executed instruction will be executed soon again
10. The spatial aspect of the locality of reference means
Correct : D. that the instruction in close proximity of the instruction executed will be executed in future
11. The correspondence between the main memory blocks and those in the cache is given by
Correct : B. mapping function
12. The algorithm to remove and place new contents into the cache is called
Correct : A. replacement algorithm
13. The write-through procedure is used
Correct : C. to write directly on the memory and the cache simultaneously
14. The bit used to signify that the cache location is updated is
Correct : A. dirty bit
15. The copy-back protocol is used
Correct : B. to update the contents of the memory from the cache
16. The approach where the memory contents are transferred directly to the processor from the memory is called
Correct : C. early-start
17. In protocol the information is directly written into the main memory.
Correct : A. write through
18. The only draw back of using the early start protocol is
Correct : B. complexity of circuit
19. During a write operation if the required block is not present in the cache then occurs.
Correct : D. write miss
20. While using the direct mapping technique, in a 16 bit system the higher order 5 bits are used for
Correct : A. tag
21. In direct mapping the presence of the block in memory is checked with the help of block field.
Correct : B. false
22. In associative mapping, in a 16 bit system the tag field has bits.
Correct : A. 12
23. The associative mapping is costlier than direct mapping.
Correct : A. true
24. The technique of searching for a block by going through all the tags is
Correct : C. associative search
25. The set-associative map technique is a combination of the direct and associative technique.
Correct : A. true
26. In set-associative technique, the blocks are grouped into sets.
Correct : D. 6
27. A control bit called has to be provided to each block in set- associative.
Correct : B. valid bit
28. The bit used to indicate whether the block was recently used or not is
Correct : D. dirty bit
29. Data which is not up-to date is called as
Correct : B. stale data
30. The main memory is structured into modules each with its own address register called
Correct : A. abr
31. When consecutive memory locations are accessed only one module is accessed at a time.
Correct : A. true
32. In memory interleaving, the lower order bits of the address is used to
Correct : B. get the address of the module
33. The number successful accesses to memory stated as a fraction is called as
Correct : A. hit rate
34. The number failed attempts to access memory, stated in the form of a fraction is called as
Correct : B. miss rate
35. In associative mapping during LRU, the counter of the new block is set to ‘0’ and all the others are incremented by one, when occurs.
Correct : B. miss
36. In LRU, the referenced blocks counter is set to’0′ and that of the previous blocks are incremented by one and others remain same, in the case of
Correct : A. hit
37. If hit rates are well below 0.9, then they’re called as speedy computers.
Correct : B. false
38. The extra time needed to bring the data into memory in case of a miss is called as
Correct : C. miss penalty
39. The miss penalty can be reduced by improving the mechanisms for data transfer between the different levels of hierarchy.
Correct : A. true
40. The CPU is also called as
Correct : B. isp
41. A common strategy for performance is making various functional units operate parallelly.
Correct : A. true
42. The PC gets incremented
Correct : C. after the fetch cycle
43. Which register in the processor is single directional?
Correct : A. mar
44. The transparent register/s is/are
Correct : D. all of the mentioned
45. Which register is connected to the MUX?
Correct : A. y
46. The registers, ALU and the interconnecting path together are called as
Correct : C. data path
47. The input and output of the registers are governed by
Correct : D. switches
48. When two or more clock cycles are used to complete data transfer it is called as
Correct : B. multi-phase clocking
49. signal is used to show complete of memory operation.
Correct : A. mfc
50. signal enables the processor to wait for the memory operation to complete.
Correct : C. wmfc
51. The small extremely fast, RAM’s all called as
Correct : B. heaps
52. To extend the connectivity of the processor bus we use
Correct : A. pci bus
53. The bus used to connect the monitor to the CPU is
Correct : B. scsi bus
54. ANSI stands for
Correct : A. american national standards institute
55. The general purpose registers are combined into a block called as
Correct : C. register file
56. In technology, the implementation of the register file is by using an array of memory locations.
Correct : A. vlsi
57. In a three BUS architecture, how many input and output ports are there?
Correct : C. 2 output and 1 input
58. CISC stands for
Correct : C. complex instruction set computer
59. There exists a separate block consisting of various units to decode an instruction.
Correct : A. true
60. There exists a separate block to increment the PC in multiple BUS organisation.
Correct : A. true
61. are the different type/s of generating control signals.
Correct : D. both micro-programmed and hardwired
62. The type of control signal is generated based on
Correct : D. all of the mentioned
63. What does the hardwired control generator consist of?
Correct : D. all of the mentioned
64. What does the end instruction do?
Correct : C. it starts a new instruction fetch cycle and resets the counter
65. BR…
Correct : A. true
66. The name hardwired came because the sequence of operations carried out is determined by the wiring.
Correct : A. true
67. The benefit of using this approach is
Correct : D. it increases the speed of operation
68. The disadvantage/s of the hardwired approach is
Correct : D. less flexible & cannot be used for complex instructions
69. In micro-programmed approach, the signals are generated by
Correct : A. machine instructions
70. A word whose individual bits represent a control signal is
Correct : B. control word
71. A sequence of control words corresponding to a control sequence is called
Correct : A. micro routine
72. Individual control words of the micro routine are called as
Correct : C. micro instruction
73. The special memory used to store the micro routines of a computer is
Correct : B. control store
74. Every time a new instruction is loaded into IR the output of is loaded into UPC.
Correct : A. starting address generator
75. The case/s where micro-programmed can perform well
Correct : D. none of the mentioned
76. The signals are grouped such that mutually exclusive signals are put together.
Correct : A. true
77. Highly encoded schemes that use compact codes to specify a small number of functions in each micro instruction is
Correct : B. vertical organisation
78. The directly mapped cache no replacement algorithm is required.
Correct : A. true
79. In associative mapping during LRU, the counter of the new block is set to ‘0’ and all the others are incremented by one when occurs.
Correct : B. miss
80. In set associative and associative mapping there exists less flexibility.
Correct : B. false
81. The algorithm which replaces the block which has not been referenced for a while is called
Correct : A. lru
82. The algorithm which removes the recently used page first is
Correct : B. mru
83. The LRU can be improved by providing a little randomness in the access.
Correct : A. true
84. The counter that keeps track of how many times a block is most likely used is
Correct : B. reference counter
85. The key factor/s in commercial success of a computer is/are
Correct : D. both performance and cost
86. A common measure of performance is
Correct : A. price/performance ratio
87. The performance depends on
Correct : B. the speed of fetch and execution
88. The main purpose of having memory hierarchy is to
Correct : D. reduce access time & provide large capacity
89. The memory transfers between two variable speed devices are always done at the speed of the faster device.
Correct : A. true
90. An effective to introduce parallelism in memory access is by
Correct : A. memory interleaving
91. The performance of the system is greatly influenced by increasing the level 1 cache.
Correct : A. true
92. Two processors A and B have clock frequencies of 700 Mhz and 900 Mhz respectively. Suppose A can execute an instruction with an average of 3 steps and B can execute with an average of 5 steps. For the execution of the same instruction which processor is faster.
Correct : A. a
93. If the instruction Add R1, R2, R3 is executed in a system which is pipelined, then the value of S is (Where S is a term of the Basic performance equation).
Correct : C. ~1
94. The physical memory is not as large as the address space spanned by the processor.
Correct : A. true
95. The program is divided into operable parts called as
Correct : B. segments
96. The techniques which move the program blocks to or from the physical memory is called as
Correct : B. virtual memory organisation
97. The binary address issued to data or instructions are called as
Correct : D. logical address
98. is used to implement virtual memory organisation.
Correct : C. mmu
99. translates the logical address into a physical address.
Correct : A. mmu
100. The DMA doesn’t make use of the MMU for bulk data transfers.