Quiznetik

Computer Architecture | Set 5

1. The bit present in the op code, indicating which of the operands is the source is called as

Correct : C. direction bit

2. The instruction used to cause unconditional jump is

Correct : C. jmp

3. instruction is used to check the bit of the condition flags.

Correct : D. bt

4. .data directive is used

Correct : B. to indicate the beginning of the data section

5. The instruction used to multiply operands yielding a double integer outcome is

Correct : B. imul

6. SIMD stands for

Correct : A. single instruction multiple data

7. In case of multimedia extension instructions, the pixels are encoded into a data item of

Correct : D. 8 bit

8. The MMX (Multimedia Extension) operands are stored in

Correct : C. float point registers

9. The division operation in IA-32 is a single operand instruction so it is assumed that

Correct : A. the divisor is stored in the eax register

10. Any condition that causes a processor to stall is called as

Correct : A. hazard

11. The stalling of the processor due to the unavailability of the instructions is called as

Correct : A. control hazard

12. The contention for the usage of a hardware device is called

Correct : A. structural hazard

13. The pipeline bubbling is a method used to prevent data hazard and structural hazards.

Correct : A. true

14. method is used in centralized systems to perform out of order execution.

Correct : B. score boarding

15. The algorithm followed in most of the systems to perform out of order execution is

Correct : A. tomasulo algorithm

16. The problem where process concurrency becomes an issue is called as

Correct : D. reader-writer problem

17. The set of loosely connected computers are called as

Correct : D. cluster

18. Each computer in a cluster is connected using

Correct : B. rj-45

19. The computer cluster architecture emerged as a result of

Correct : D. distributed systems

20. The software which governs the group of computers is

Correct : C. clustering middleware

21. The cluster formation in which the work is divided equally among the systems is

Correct : A. load-configuration

22. In the client server model of the cluster                     approach is used.

Correct : D. round robin

23. The most common modes of communication in clusters are

Correct : D. both message passing interface and pvm

24. The method followed in case of node failure, wherein the node gets disabled is

Correct : A. stonith

25. VLIW stands for?

Correct : A. very long instruction word

26. The main difference between the VLIW and the other approaches to improve performance is

Correct : C. lack of complex hardware design

27. In VLIW the decision for the order of execution of the instructions depends on the program itself.

Correct : A. true

28. The parallel execution of operations in VLIW is done according to the schedule determined by

Correct : C. compiler

29. The VLIW processors are much simpler as they do not require of

Correct : D. scheduling hardware

30. To compute the direction of the branch the VLIW uses

Correct : B. heuristics

31. EPIC stands for?

Correct : A. explicitly parallel instruction computing

32. The duration between the read and the mfc signal is

Correct : A. access time

33. The minimum time delay between two successive memory read operations is

Correct : A. cycle time

34. is the bottleneck, when it comes computer performance.

Correct : B. memory cycle time

35. The logical addresses generated by the cpu are mapped onto physical memory by

Correct : C. mmu

36. VLSI stands for

Correct : A. very large scale integration

37. The cells in a row are connected to a common line called

Correct : B. word line

38. The cells in each column are connected to

Correct : D. sense/ write line

39. The word line is driven by the

Correct : B. address decoder

40. A 16 X 8 Organisation of memory cells, can store upto

Correct : D. 128 bits

41. A memory organisation that can hold upto 1024 bits and has a minimum of 10 address lines can be organized into

Correct : D. 1024 x 1

42. Circuits that can hold their state as long as power is applied is

Correct : B. static memory

43. The number of external connections required in 16 X 8 memory organisation is

Correct : A. 14

44. The advantage of CMOS SRAM over the transistor one’s is

Correct : D. low power consumption

45. In a 4M-bit chip organisation has a total of 19 external connections.then it has                 address if 8 data lines are there.

Correct : C. 9

46. The Reason for the disregarding of the SRAM’s is

Correct : C. high cost

47. The disadvantage of DRAM over SRAM is/are

Correct : C. the cells are not static

48. The reason for the cells to lose their state over time is

Correct : B. usage of capacitors to store the charge

49. The capacitors lose the charge over time due to

Correct : A. the leakage resistance of the capacitor

50. circuit is used to restore the capacitor value.

Correct : A. sense amplify

51. To reduce the number of external connections required, we make use of

Correct : B. multiplexer

52. The processor must take into account the delay in accessing the memory location, such memories are called

Correct : B. asynchronous memories

53. To get the row address of the required data               is enabled.

Correct : B. ras

54. In order to read multiple bytes of a row at the same time, we make use of

Correct : A. latch

55. The block transfer capability of the DRAM is called

Correct : C. fast page mode

56. The difference between DRAM’s and SDRAM’s is/are

Correct : D. none of the mentioned

57. The difference in the address and data connection between DRAM’s and SDRAM’s is

Correct : C. the usage of a buffer in sdram’s

58. A                 is used to restore the contents of the cells.

Correct : B. refresh counter

59. The mode register is used to

Correct : B. select the mode of operation

60. In a SDRAM each row is refreshed every 64ms.

Correct : A. true

61. DDR SDRAM’s perform faster data transfer by

Correct : B. transferring on both edges

62. To improve the data retrieval rate

Correct : C. memory latency

63. In SDRAM’s buffers are used to store data that is read or written.

Correct : A. true

64. The SDRAM performs operation on the

Correct : A. rising edge of the clock

65. The chip can be disabled or cut off from an external connection using

Correct : A. chip select

66. To organise large memory chips we make use of

Correct : C. memory modules

67. The less space consideration as lead to the development of                   (for large memories).

Correct : D. both simm’s and dims’s

68. The SRAM’s are basically used as

Correct : B. caches

69. The higher order bits of the address are used to

Correct : A. specify the row address

70. The address lines multiplexing is done using

Correct : B. memory controller unit

71. The controller multiplexes the addresses after getting the            signal.

Correct : D. request

72. The RAS and CAS signals are provided by the

Correct : C. memory controller

73. When DRAM’s are used to build a complex large memory, then the controller only provides the refresh counter.

Correct : A. true

74. RAMBUS is better than the other memory chips in terms of

Correct : B. speed of operation

75. The key feature of the RAMBUS tech is

Correct : C. speed of transfer

76. The increase in operation speed is done by

Correct : A. reducing the reference voltage

77. The data is transferred over the RAMBUS as

Correct : C. swing voltages

78. The type of signaling used in RAMBUS is

Correct : B. differential signaling

79. The special communication used in RAMBUS are

Correct : A. rambus channel

80. The original design of the RAMBUS required for                   data lines.

Correct : D. 9

81. The RAMBUS requires specially designed memory chips similar to

Correct : C. dram

82. A RAMBUS which has 18 data lines is called as

Correct : B. direct rambus

83. The RDRAM chips assembled into larger memory modules called

Correct : A. rrim

84. If the transistor gate is closed, then the ROM stores a value of 1.

Correct : B. false

85. PROM stands for

Correct : A. programmable read only memory

86. The PROM is more effective than ROM chips in regard to

Correct : D. both cost and speed of operation

87. The difference between the EPROM and ROM circuitry is

Correct : C. the usage of an extra transistor

88. The ROM chips are mainly used to store

Correct : C. boot files

89. The contents of the EPROM are erased by

Correct : B. exposing the chip to uv rays

90. The disadvantage of the EPROM chip is

Correct : D. the need to remove the chip physically to reprogram it

91. EEPROM stands for Electrically Erasable Programmable Read Only Memory.

Correct : A. true

92. The memory devices which are similar to EEPROM but differ in the cost effectiveness is

Correct : C. flash memory

93. The only difference between the EEPROM and flash memory is that the latter doesn’t allow bulk data to be written.

Correct : A. true

94. The flash memories find application in

Correct : D. portable devices

95. The flash memory modules designed to replace the functioning of a hard disk is

Correct : B. flash drives

96. The reason for the fast operating speeds of the flash drives is

Correct : A. the absence of any movable parts

97. The standard SRAM chips are costly as

Correct : B. they house 6 transistor per chip

98. The drawback of building a large memory with DRAM is

Correct : C. the slow speed of operation

99. To overcome the slow operating speeds of the secondary memory we make use of faster flash drives.

Correct : A. true

100. The fastest data access is provided using

Correct : D. registers