Quiznetik
Computer Architecture | Set 4
1. constitute the representation of the floating number.
A. sign
B. significant digits
C. scale factor
D. all of the mentioned
Correct : D. all of the mentioned
2. The sign followed by the string of digits is called as
A. significant
B. determinant
C. mantissa
D. exponent
Correct : C. mantissa
3. The normalized representation of 0.0010110 * 2 9 is
A. 0 10001000 0010110
B. 0 10000101 0110
C. 0 10101010 1110
D. 0 11110100 11100
Correct : B. 0 10000101 0110
4. The 32 bit representation of the decimal number is called as
A. double-precision
B. single-precision
C. extended format
D. none of the mentioned
Correct : B. single-precision
5. In 32 bit representation the scale factor as a range of
A. -128 to 127
B. -256 to 255
C. 0 to 255
D. none of the mentioned
Correct : A. -128 to 127
6. In double precision format, the size of the mantissa is
A. 32 bit
B. 52 bit
C. 64 bit
D. 72 bit
Correct : B. 52 bit
7. have been developed specifically for pipelined systems.
A. utility software
B. speed up utilities
C. optimizing compilers
D. none of the mentioned
Correct : C. optimizing compilers
8. The pipelining process is also called as
A. superscalar operation
B. assembly line operation
C. von neumann cycle
D. none of the mentioned
Correct : B. assembly line operation
9. To increase the speed of memory access in pipelining, we make use of
A. modification in processor architecture
B. clock
C. special unit
D. control unit
Correct : B. clock
10. Each stage in pipelining should be completed within cycle.
A. 1
B. 2
C. 3
D. 4
Correct : A. 1
11. In pipelining the task which requires the least time is performed first.
A. true
B. false
Correct : B. false
12. If a unit completes its task before the allotted time period, then
A. special memory locations
B. special purpose registers
C. cache
D. buffers
Correct : C. cache
13. The periods of time when the unit is idle is called as
A. stalls
B. bubbles
C. hazards
D. both stalls and bubbles
Correct : D. both stalls and bubbles
14. The throughput of a super scalar processor is
A. less than 1
B. 1
C. more than 1
D. not known
Correct : C. more than 1
15. When the processor executes multiple instructions at a time it is said to use
A. single issue
B. multiplicity
C. visualization
D. multiple issues
Correct : D. multiple issues
16. The plays a very vital role in case of super scalar processors.
A. compilers
B. motherboard
C. memory
D. peripherals
Correct : A. compilers
17. If an exception is raised and the succeeding instructions are executed completely, then the processor is said to have
A. exception handling
B. imprecise exceptions
C. error correction
D. none of the mentioned
Correct : B. imprecise exceptions
18. In super-scalar mode, all the similar instructions are grouped and executed together.
A. true
B. false
Correct : A. true
19. Since it uses the out of order mode of execution, the results are stored in
A. buffers
B. special memory locations
C. temporary registers
D. tlb
Correct : C. temporary registers
20. The step where in the results stored in the temporary register is transferred into the permanent register is called as
A. final step
B. commitment step
C. last step
D. inception step
Correct : B. commitment step
21. A special unit used to govern the out of order execution of the instructions is called as
A. commitment unit
B. temporal unit
C. monitor
D. supervisory unit
Correct : A. commitment unit
22. The commitment unit uses a queue called
A. record buffer
B. commitment buffer
C. storage buffer
D. none of the mentioned
Correct : A. record buffer
23. The CISC stands for
A. computer instruction set compliment
B. complete instruction set compliment
C. computer indexed set components
D. complex instruction set computer
Correct : D. complex instruction set computer
24. The computer architecture aimed at reducing the time of execution of instructions is
A. cisc
B. risc
C. isa
D. anna
Correct : B. risc
25. The Sun micro systems processors usually follow architecture.
A. cisc
B. isa
C. ultra sparc
D. risc
Correct : D. risc
26. The RISC processor has a more complicated design than CISC.
A. true
B. false
Correct : B. false
27. The iconic feature of the RISC machine among the following is
A. reduced number of addressing modes
B. increased memory size
C. having a branch delay slot
D. all of the mentioned
Correct : C. having a branch delay slot
28. Both the CISC and RISC architectures have been developed to reduce the
A. cost
B. time delay
C. semantic gap
D. all of the mentioned
Correct : C. semantic gap
29. Pipe-lining is a unique feature of
A. risc
B. cisc
C. isa
D. iana
Correct : A. risc
30. In CISC architecture most of the complex instructions are stored in
A. register
B. diodes
C. cmos
D. transistors
Correct : D. transistors
31. Which of the architecture is power efficient?
A. cisc
B. risc
C. isa
D. iana
Correct : B. risc
32. For converting a virtual address into the physical address, the programs are divided into
A. pages
B. frames
C. segments
D. blocks
Correct : A. pages
33. The memory allocated to each page is contiguous.
A. true
B. false
Correct : A. true
34. The pages size shouldn’t be too small, as this would lead to
A. transfer errors
B. increase in operation time
C. increase in access time
D. decrease in performance
Correct : C. increase in access time
35. The cache bridges the speed gap between and
A. ram and rom
B. ram and secondary memory
C. processor and ram
D. none of the mentioned
Correct : C. processor and ram
36. The virtual memory bridges the size and speed gap between and
A. ram and rom
B. ram and secondary memory
C. processor and ram
D. none of the mentioned
Correct : B. ram and secondary memory
37. The higher order bits of the virtual address generated by the processor forms the
A. table number
B. frame number
C. list number
D. page number
Correct : D. page number
38. The page length shouldn’t be too long because
A. it reduces the program efficiency
B. it increases the access time
C. it leads to wastage of memory
D. none of the mentioned
Correct : C. it leads to wastage of memory
39. The lower order bits of the virtual address forms the
A. page number
B. frame number
C. block number
D. offset
Correct : D. offset
40. The area in the main memory that can hold one page is called as
A. page entry
B. page frame
C. frame
D. block
Correct : B. page frame
41. The starting address of the page table is stored in
A. tlb
B. r0
C. page table base register
D. none of the mentioned
Correct : C. page table base register
42. The bits used to indicate the status of the page in the memory is called
A. control bits
B. status bits
C. progress bit
D. none of the mentioned
Correct : A. control bits
43. The bit is used to indicate the validity of the page.
A. valid bit
B. invalid bit
C. correct bit
D. none of the mentioned
Correct : A. valid bit
44. The bit used to store whether the page has been modified or not is called as
A. dirty bit
B. modify bit
C. relocation bit
D. none of the mentioned
Correct : A. dirty bit
45. The page table should be ideally situated within
A. processor
B. tlb
C. mmu
D. cache
Correct : C. mmu
46. If the page table is large then it is stored in
A. processor
B. main memory
C. disk
D. secondary storage
Correct : B. main memory
47. When the page table is placed in the main memory, the is used to store the recently accessed pages.
A. mmu
B. tlb
C. r0
D. table
Correct : B. tlb
48. The TLB is incorporated as part of the
A. processor
B. mmu
C. disk
D. ram
Correct : B. mmu
49. Whenever a request to the page that is not present in the main memory is accessed is triggered.
A. interrupt
B. request
C. page fault
D. none of the mentioned
Correct : C. page fault
50. What does the RUN signal do?
A. it causes the termination of a signal
B. it causes a particular signal to perform its operation
C. it causes a particular signal to end
D. it increments the step counter by one
Correct : D. it increments the step counter by one
51. register is designated to point to the 68000 processor stack.
A. a7 register
B. b2 register
C. there is no such designation
D. any general purpose register is selected at random
Correct : A. a7 register
52. The word length in the 68000 computer is
A. 32 bit
B. 64 bit
C. 16 bit
D. 8 bit
Correct : C. 16 bit
53. Is 68000 computer Byte addressable?
A. true
B. false
Correct : A. true
54. The register in 68000 can contain up to bits.
A. 24
B. 32
C. 16
D. 64
Correct : B. 32
55. The 68000 has a max of how many data registers?
A. 16
B. 20
C. 10
D. 8
Correct : D. 8
56. When an operand is stored in a register it is
A. stored in the lower order bits of the register
B. stored in the higher order bits of the register
C. stored in any of the bits at random
D. none of the mentioned
Correct : A. stored in the lower order bits of the register
57. The 68000 uses address assignment.
A. big endian
B. little endian
C. x-little endian
D. x-big endian
Correct : A. big endian
58. The addresses generated by the 68000 is bit.
A. 32
B. 16
C. 24
D. 42
Correct : C. 24
59. Instructions which can handle any type of addressing mode are said to be
A. omniscient
B. orthogonal
C. versatile
D. none of the mentioned
Correct : B. orthogonal
60. The instructions in 68000 can deal with operands of three different sizes.
A. true
B. false
Correct : A. true
61. The Branch instruction in 68000 provides how many types of offsets?
A. 3
B. 1
C. 0
D. 2
Correct : D. 2
62. The 68000 uses method to access I/O devices buffers.
A. memory mapped
B. i/o mapped
C. buffer mapped
D. none of the mentioned
Correct : A. memory mapped
63. instruction is used to set up a frame pointer for the subroutines in 68000.
A. create
B. link
C. unlk
D. frame
Correct : B. link
64. The LINK instruction is always followed by instruction.
A. mov
B. unlk
C. org
D. movem
Correct : D. movem
65. ARM stands for
A. advanced rate machines
B. advanced risc machines
C. artificial running machines
D. aviary running machines
Correct : B. advanced risc machines
66. The main importance of ARM micro- processors is providing operation with
A. low cost and low power consumption
B. higher degree of multi-tasking
C. lower error or glitches
D. efficient memory management
Correct : A. low cost and low power consumption
67. ARM processors where basically designed for
A. main frame systems
B. distributed systems
C. mobile systems
D. super computers
Correct : C. mobile systems
68. The ARM processors don’t support Byte addressability.
A. true
B. false
Correct : B. false
69. The address space in ARM is
A. 224
B. 264
C. 216
D. 232
Correct : D. 232
70. The address system supported by ARM systems is/are
A. little endian
B. big endian
C. x-little endian
D. both little & big endian
Correct : D. both little & big endian
71. RISC stands for
A. restricted instruction sequencing computer
B. restricted instruction sequential compiler
C. reduced instruction set computer
D. reduced induction set computer
Correct : C. reduced instruction set computer
72. In the ARM, PC is implemented using
A. caches
B. heaps
C. general purpose register
D. stack
Correct : C. general purpose register
73. The additional duplicate register used in ARM machines are called as
A. copied-registers
B. banked registers
C. extra registers
D. extential registers
Correct : B. banked registers
74. The banked registers are used for
A. switching between supervisor and interrupt mode
B. extended storing
C. same as other general purpose registers
D. none of the mentioned
Correct : A. switching between supervisor and interrupt mode
75. Each instruction in ARM machines is encoded into Word.
A. 2 byte
B. 3 byte
C. 4 byte
D. 8 byte
Correct : C. 4 byte
76. All instructions in ARM are conditionally executed.
A. true
B. false
Correct : A. true
77. The addressing mode where the EA of the operand is the contents of Rn is
A. pre-indexed mode
B. pre-indexed with write back mode
C. post-indexed mode
D. none of the mentioned
Correct : C. post-indexed mode
78. The effective address of the instruction written in Post-indexed mode, MOVE[Rn]+Rm is
A. ea = [rn]
B. ea = [rn + rm]
C. ea = [rn] + rm
D. ea = [rm] + rn
Correct : A. ea = [rn]
79. symbol is used to signify write back mode.
A. #
B. ^
C. &
D. !
Correct : D. !
80. The instruction, MLA R0,R1,R2,R3 performs
A. r0<-[r1]+[r2]+[r3]
B. r3<-[r0]+[r1]+[r2]
C. r0<-[r1]*[r2]+[r3]
D. r3<-[r0]*[r1]+[r2]
Correct : C. r0<-[r1]*[r2]+[r3]
81. instruction is used to get the 1’s complement of the operand.
A. comp
B. bic
C. ~cmp
D. mvn
Correct : D. mvn
82. The offset used in the conditional branching is bit.
A. 24
B. 32
C. 16
D. 8
Correct : A. 24
83. The condition to check whether the branch should happen or not is given by
A. the lower order 8 bits of the instruction
B. the higher order 4 bits of the instruction
C. the lower order 4 bits of the instruction
D. the higher order 8 bits of the instruction
Correct : B. the higher order 4 bits of the instruction
84. directive is used to indicate the beginning of the program instruction or data.
A. equ
B. start
C. area
D. space
Correct : C. area
85. directive specifies the start of the execution.
A. start
B. entry
C. main
D. origin
Correct : B. entry
86. directives are used to initialize operands.
A. int
B. dataword
C. reserve
D. dcd
Correct : D. dcd
87. directive is used to name the register used for execution of an instruction.
A. assign
B. rn
C. name
D. declare
Correct : B. rn
88. The pseudo instruction used to load an address into the register is
A. load
B. adr
C. assign
D. psload
Correct : B. adr
89. The size of the floating registers can be extended upto
A. 128 bit
B. 256 bit
C. 80 bit
D. 64 bit
Correct : C. 80 bit
90. The floating point numbers are stored in general purpose register in IA-32.
A. true
B. false
Correct : B. false
91. The PC is incorporated with the help of general purpose registers.
A. true
B. false
Correct : B. false
92. IOPL stands for
A. input/output privilege level
B. input output process link
C. internal output process link
D. internal offset privilege level
Correct : A. input/output privilege level
93. In IA-32 architecture along with the general flags, the other conditional flags provided are
A. iopl
B. if
C. tf
D. all of the mentioned
Correct : D. all of the mentioned
94. The register used to serve as PC is called as
A. indirection register
B. instruction pointer
C. r-32
D. none of the mentioned
Correct : B. instruction pointer
95. The IA-32 processor can switch between 16 bit operation and 32 bit operation with the help of instruction prefix bit.
A. true
B. false
Correct : A. true
96. The Bit extension of the register is denoted with the help of symbol.
A. $
B. `
C. e
D. ~
Correct : C. e
97. The instruction, ADD R1, R2, R3 is decoded as
A. r1<-[r1]+[r2]+[r3]
B. r3<-[r1]+[r2]
C. r3<-[r1]+[r2]+[r3]
D. r1<-[r2]+[r3]
Correct : D. r1<-[r2]+[r3]
98. The instruction JG loop does
A. jumps to the memory location loop if the result of the most recent arithmetic op is even
B. jumps to the memory location loop if the result of the most recent arithmetic op is greater than 0
C. jumps to the memory location loop if the test condition is satisfied with the value of loop
D. none of the mentioned
Correct : B. jumps to the memory location loop if the result of the most recent arithmetic op is greater than 0
99. The LEA mnemonic is used to
A. load the effective address of an instruction
B. load the values of operands onto an accumulator
C. declare the values as global constants
D. store the outcome of the operation at a memory location
Correct : A. load the effective address of an instruction
100. The instructions of IA-32 machines are of length up to
A. 4 bytes
B. 8 bytes
C. 16 bytes
D. 12 bytes
Correct : D. 12 bytes