Quiznetik

Computer Architecture | Set 2

1. What is subroutine nesting?

Correct : C. having one routine call the other

2. The order in which the return addresses are generated and used is

Correct : A. lifo

3. In case of nested subroutines the return addresses are stored in

Correct : C. processor stack

4. The appropriate return addresses are obtained with the help of          in case of nested routines.

Correct : D. stack-pointers

5. When parameters are being passed on to the subroutines they are stored in

Correct : D. all of the mentioned

6. The most efficient way of handling parameter passing is by using

Correct : A. general purpose registers

7. The most Flexible way of logging the return addresses of the subroutines is by using

Correct : B. stacks

8. The private work space dedicated to a subroutine is called as

Correct : C. stack frame

9. If the subroutine exceeds the private space allocated to it then the values are pushed onto

Correct : A. stack

10. pointer is used to point to parameters passed or local parameters of the subroutine.

Correct : B. frame pointer

11. The reserved memory or private space of the subroutine gets deallocated when

Correct : C. when the routine’s return statement is executed

12. The private space gets allocated to each subroutine when

Correct : C. when the routine gets called

13. the most suitable data structure used to store the return addresses in the case of nested subroutines.

Correct : B. stack

14. In the case of nested subroutines, the stack top is always

Correct : A. the saved contents of the called sub routine

15. The stack frame for each subroutine is present in

Correct : C. processor stack

16. The data structure suitable for scheduling processes is

Correct : C. queue

17. The sub-routine service procedure is similar to that of the interrupt service routine in

Correct : D. method of context switch & process execution

18. In memory-mapped I/O

Correct : A. the i/o devices and the memory share the same address space

19. The usual BUS structure used to connect the I/O devices is

Correct : C. single bus structure

20. In intel’s IA-32 architecture there is a separate 16 bit address space for the I/O devices.

Correct : B. true

21. The system is notified of a read or write operation by

Correct : D. sending a special signal along the bus

22. To overcome the lag in the operating speeds of the I/O device and the processor we use

Correct : B. status flags

23. The method of accessing the I/O devices by repeatedly checking the status flags is

Correct : A. program-controlled i/o

24. The method of synchronising the processor with the I/O device in which the device sends a signal when it is ready is?

Correct : C. interrupts

25. The interrupt-request line is a part of the

Correct : B. control line

26. The method which offers higher speeds of I/O transfers is

Correct : D. dma

27. The signal sent to the device from the processor to the device after receiving an interrupt is

Correct : A. interrupt-acknowledge

28. The time between the receiver of an interrupt and its service is

Correct : B. interrupt latency

29. A single Interrupt line can be used to service n different devices.

Correct : A. true

30. The resistor which is attached to the service line is called

Correct : B. pull-up resistor

31. An interrupt that can be temporarily ignored is

Correct : C. maskable interrupt

32. Which interrupt is unmaskable?

Correct : C. trap

33. When dealing with multiple devices interrupts, which mechanism is easy to implement?

Correct : A. polling method

34. The interrupt servicing mechanism in which the requesting device identifies itself to the processor to be serviced is

Correct : B. vectored interrupts

35. In vectored interrupts, how does the device identify itself to the processor?

Correct : C. by sending the starting address of the service routine

36. The code sent by the device in vectored interrupt is            long.

Correct : D. 4-8 bits

37. The starting address sent by the device in vectored interrupt is called as

Correct : B. interrupt vector

38. The processor indicates to the devices that it is ready to receive interrupts

Correct : C. by activating the interrupt acknowledge line

39. Which table handle stores the addresses of the interrupt handling sub- routines?

Correct : A. interrupt-vector table

40. method is used to establish priority by serially connecting all devices that request an interrupt.

Correct : B. daisy chain

41. In daisy chaining device 0 will pass the signal only if it has

Correct : B. no interrupt request

42. interrupt method uses register whose bits are set separately by interrupt signal for each device.

Correct : A. parallel priority interrupt

43. register is used for the purpose of controlling the status of each interrupt request in parallel priority interrupt.

Correct : D. mask

44. The added output of the bits of the interrupt register and the mask register is set as an input of

Correct : B. priority encoder

45. Interrupts initiated by an instruction is called as

Correct : B. external

46. If during the execution of an instruction an exception is raised then

Correct : B. the instruction is halted and the exception is handled

47. is/are types of exceptions.

Correct : D. all of the mentioned

48. The program used to find out errors is called

Correct : A. debugger

49. The two facilities provided by the debugger is

Correct : D. both trace and break points

50. In trace mode of operation is

Correct : A. the program is interrupted after each detection

51. What are the different modes of operation of a computer?

Correct : B. user and supervisor mode

52. The instructions which can be run only supervisor mode are?

Correct : C. privileged instructions

53. How is a privilege exception dealt with?

Correct : A. the program is halted and the system switches into supervisor mode and restarts the program execution

54. The DMA differs from the interrupt mode by

Correct : D. none of the mentioned

55. The DMA transfers are performed by a control circuit called as

Correct : B. dma controller

56. In DMA transfers, the required signals and addresses are given by the

Correct : C. dma controllers

57. After the completion of the DMA transfer, the processor is notified by

Correct : B. interrupt signal

58. When the R/W bit of the status register of the DMA controller is set to 1.

Correct : A. read operation is performed

59. The controller is connected to the

Correct : B. system bus

60. Can a single DMA controller perform operations on two different disks simultaneously?

Correct : A. true

61. The technique whereby the DMA controller steals the access cycles of the processor to operate is called

Correct : C. cycle stealing

62. The technique where the controller is given complete access to main memory is

Correct : D. burst mode

63. The controller uses            to help with the transfers when handling network interfaces.

Correct : A. input buffer storage

64. To overcome the conflict over the possession of the BUS we use

Correct : B. bus arbitrators

65. The registers of the controller are

Correct : C. 32 bits

66. When the process requests for a DMA transfer?

Correct : D. process is temporarily suspended & another process gets executed

67. The DMA transfer is initiated by

Correct : C. i/o devices

68. To resolve the clash over the access of the system BUS we use

Correct : B. bus arbitrator

69. The device which is allowed to initiate data transfers on the BUS at any time is called

Correct : A. bus master

70. BUS arbitration approach uses the involvement of the processor.

Correct : A. centralised arbitration

71. The circuit used for the request line is a

Correct : C. open-drain

72. The Centralised BUS arbitration is

Correct : B. bus grant signal

73. Once the BUS is granted to a device

Correct : A. it activates the bus busy line

74. When the processor receives the request from a device, it responds by sending

Correct : B. open-collector circuit

75. After the device completes its operation            assumes the control of the BUS.

Correct : B. processor

76. The BUS busy line is used

Correct : C. to indicate the bus is already allocated

77. If two devices A and B contesting for the BUS have ID’s 5 and 6 respectively, which device gets the BUS based on the Distributed arbitration.

Correct : B. device b

78. In Distributed arbitration, the device requesting the BUS

Correct : A. asserts the start arbitration signal

79. How is a device selected in Distributed arbitration?

Correct : A. to connect the various devices to the cpu

80. The device which starts data transfer is called

Correct : D. initiator

81. The device which interacts with the initiator is

Correct : A. slave

82. In synchronous BUS, the devices get the timing signals from

Correct : B. a common clock line

83. The delays caused in the switching of the timing signals is due to

Correct : C. propagation delay

84. The time for which the data is to be on the BUS is affected by

Correct : D. propagation delay of the circuit & setup time of the device

85. The Master strobes the slave at the end of each clock cycle in Synchronous BUS.

Correct : A. true

86. Which is fed into the BUS first by the initiator?

Correct : D. address, commands or controls

87. The devices with variable speeds are usually connected using asynchronous BUS.

Correct : A. true

88. The MSYN signal is initiated

Correct : B. soon after the decoding of the address

89. In IBM’s S360/370 systems            lines are used to select the I/O devices.

Correct : A. scan in and out

90. The meter in and out lines are used for

Correct : A. monitoring the usage of devices

91. MRDC stands for

Correct : B. memory ready command

92. The BUS that allows I/O, memory and Processor to coexist is

Correct : C. backplane bus

93. The transmission on the asynchronous BUS is also called

Correct : D. hand-shake transmission

94. Asynchronous mode of transmission is suitable for systems with multiple peripheral devices.

Correct : A. true

95. The asynchronous BUS mode of transmission allows for a faster mode of data transfer.

Correct : B. false

96. serves as an intermediary between the device and the BUSes.

Correct : A. interface circuits

97. The side of the interface circuits, that has the data path and the control signals to transfer data between interface and device is

Correct : B. port side

98. What is the interface circuit?

Correct : C. helps in the decoding of the address on the address bus

99. The conversion from parallel to serial data transmission and vice versa takes place inside the interface circuits.

Correct : A. true

100. The Interface circuits generate the appropriate timing signals required by the BUS control scheme.

Correct : A. true