Quiznetik
Microprocessor and Assembly Language Programming | Set 1
1. A microprocessor is a _______ chip integrating all the functions of a CPU of a computer.
A. multiple
B. single
C. double
D. triple
Correct : B. single
2. Microprocessor is a/an _______ circuit that functions as the CPU of the compute
A. electronic
B. mechanic
C. integrating
D. processing
Correct : A. electronic
3. Microprocessor is the ______ of the computer and it perform all the computational tasks
A. main
B. heart
C. important
D. simple
Correct : B. heart
4. The purpose of the microprocessor is to control ______
A. memory
B. switches
C. processing
D. tasks
Correct : A. memory
5. The first digital electronic computer was built in the year________
A. 1950
B. 1960
C. 1940
D. 1930
Correct : C. 1940
6. In 1960's texas institute invented ______
A. integrated circuits
B. microprocessor
C. vacuum tubes
D. transistors
Correct : A. integrated circuits
7. The intel 8086 microprocessor is a _______ processor
A. 8 bit
B. 16 bit
C. 32 bit
D. 4 bit
Correct : B. 16 bit
8. The microprocessor can read/write 16 bit data from or to ________
A. memory
B. i/o device
C. processor
D. register
Correct : A. memory
9. In 8086 microprocessor , the address bus is ________ bit wide
A. 12 bit
B. 10 bit
C. 16 bit
D. 26 bit
Correct : D. 26 bit
10. The work of EU is ________
A. encoding
B. decoding
C. processing
D. calculations
Correct : B. decoding
11. The 16 bit flag of 8086 microprocessor is responsible to indicate ___________
A. the condition of result of ALU operation
B. the condition of memory
C. the result of addition
D. the result of subtraction
Correct : A. the condition of result of ALU operation
12. The CF is known as ________
A. carry flag
B. condition flag
C. common flag
D. single flag
Correct : A. carry flag
13. The SF is called as ________
A. service flag
B. sign flag
C. single flag
D. condition flag
Correct : B. sign flag
14. The OF is called as _______
A. overflow flag
B. overdue flag
C. one flag
D. over flag
Correct : A. overflow flag
15. The IF is called as _________
A. initial flag
B. indicate flag
C. interrupt flag
D. inter flag
Correct : C. interrupt flag
16. The register AX is formed by grouping ________
A. AH & AL
B. BH & BL
C. CH & CL
D. DH & DL
Correct : A. AH & AL
17. The SP is indicated by ________
A. single pointer
B. stack pointer
C. source pointer
D. destination pointer
Correct : B. stack pointer
18. The BP is indicated by _______
A. base pointer
B. binary pointer
C. bit pointer
D. digital pointer
Correct : A. base pointer
19. The SS is called as ________
A. single stack
B. stack segment
C. sequence stack
D. random stack
Correct : B. stack segment
20. The index register are used to hold _______
A. memory register
B. offset address
C. segment memory
D. offset memory
Correct : A. memory register
21. The BIU contains FIFO register of size __________ bytes
A. 8
B. 6
C. 4
D. 12
Correct : B. 6
22. The BIU prefetches the instruction from memory and store them in ________
A. queue
B. register
C. memory
D. stack
Correct : A. queue
23. The 1 MB byte of memory can be divided into ______ segment
A. 1 Kbyte
B. 64 Kbyte
C. 33 Kbyte
D. 34 Kbyte
Correct : B. 64 Kbyte
24. The DS is called as _______
A. data segment
B. digital segment
C. divide segment
D. decode segme
Correct : A. data segment
25. The CS register stores instruction _____________ in code segment
A. stream
B. path
C. codes
D. stream line
Correct : C. codes
26. The IP is ________ bits in length
A. 8 bits
B. 4 bits
C. 16 bits
D. 32 bits
Correct : C. 16 bits
27. The push source copies a word from source to ______
A. stack
B. memory
C. register
D. destination
Correct : A. stack
28. LDs copies to consecutive words from memory to register and ___________
A. ES
B. DS
C. SS
D. CS
Correct : B. DS
29. Inc destination increments the content of destination by _______
A. 1
B. 2
C. 30
D. 41
Correct : A. 1
30. IMUL source is a signed _________
A. multiplication
B. addition
C. subtraction
D. division
Correct : A. multiplication
31. _________destination inverts each bit of destination
A. NOT
B. NOR
C. AND
D. OR
Correct : A. NOT
32. The JS is called as ______
A. jump the signed bit
B. jump single bit
C. jump simple bit
D. jump signal it
Correct : A. jump the signed bit
33. Instruction providing both segment base and offset address are called _____
A. below type
B. far type
C. low type
D. high type
Correct : B. far type
34. The conditional branch instruction specify ___________ for branching
A. conditions
B. instruction
C. address
D. memory
Correct : A. conditions
35. The microprocessor determines whether the specified condition exists or not by testing the ______
A. carry flag
B. conditional flag
C. common flag
D. sign flag
Correct : B. conditional flag
36. The LES copies to words from memory to register and __________
A. DS
B. CS
C. ES
D. DS
Correct : C. ES
37. The _________ translates a byte from one code to another code
A. XLAT
B. XCHNG
C. POP
D. PUSH
Correct : A. XLAT
38. The _______ contains an offset instead of actual address
A. SP
B. IP
C. ES
D. SS
Correct : B. IP
39. The 8086 fetches instruction one after another from __________ of memory
A. code segment
B. IP
C. ES
D. SS
Correct : A. code segment
40. The BIU contains FIFO register of size 6 bytes called _____
A. queue
B. stack
C. segment
D. register
Correct : A. queue
41. The ___________ is required to synchronize the internal operands in the processor CIK Signal
A. UR Signal
B. Vcc
C. AIE
D. Ground
Correct : A. UR Signal
42. The pin of minimum mode AD0-AD15 has ____________ address
A. 16 bit
B. 20 bit
C. 32 bit
D. 4 bit
Correct : B. 20 bit
43. The pin of minimum mode AD0- AD15 has _________ data bus
A. 4 bit
B. 20 bit
C. 16 bit
D. 32 bit
Correct : C. 16 bit
44. The address bits are sent out on lines through __________
A. A16-19
B. A0-17
C. D0-D17
D. C0-C17
Correct : A. A16-19
45. ________ is used to write into memory
A. RD
B. WR
C. RD / WR
D. Chk
Correct : B. WR
46. The functions of Pins from 24 to 31 depend on the mode in which _______ is operating
A. 8085
B. 8086
C. 80835
D. 80845
Correct : B. 8086
47. The RD,WR,M/IO is the heart of control for a __________ mode
A. minimum
B. maximum
C. compatibility mode
D. control mode
Correct : A. minimum
48. In a minimum mode there is a ___________ on the system bus
A. single
B. double
C. multiple
D. triple
Correct : A. single
49. If MN/MX is low the 8086 operates in __________ mode
A. Minimum
B. Maximum
C. both (A) and (B)
D. medium
Correct : B. Maximum
50. In max mode, control bus signal So,S1 and S2 are sent out in ____________ form
A. decoded
B. encoded
C. shared
D. un shared
Correct : B. encoded
51. The ___ bus controller device decodes the signals to produce the control bus signal
A. internal
B. data
C. external
D. address
Correct : C. external
52. A _____ Instruction at the end of interrupt service program takes the execution back to the interrupted program
A. forward
B. return
C. data
D. line
Correct : B. return
53. The main concerns of the ___________ are to define a flexible set of commands
A. memory interface
B. peripheral interface
C. both (A) and (B)
D. control interface
Correct : A. memory interface
54. Primary function of memory interfacing is that the _________ should be able to read from and write into register
A. multiprocessor
B. microprocessor
C. dual Processor
D. coprocessor
Correct : B. microprocessor
55. To perform any operations, the Mp should identify the __________
A. register
B. memory
C. interface
D. system
Correct : A. register
56. The Microprocessor places __________ address on the address bus
A. 4 bit
B. 8 bit
C. 16 bit
D. 32 bit
Correct : C. 16 bit
57. The Microprocessor places 16 bit address on the add lines from that address by _____ register should be selected
A. address
B. one
C. two
D. three
Correct : B. one
58. The ________of the memory chip will identify and select the register for the EPROM
A. internal decoder
B. external decoder
C. address decoder
D. data decoder
Correct : A. internal decoder
59. Microprocessor provides signal like ____ to indicate the read operatio
A. LOW
B. MCMW
C. MCMR
D. MCMWR
Correct : C. MCMR
60. To interface memory with the microprocessor, connect register the lines of the address bus must be added to address lines of the _______ chip
A. single
B. memory
C. multiple
D. triple
Correct : B. memory
61. The remaining address line of ______ bus is decoded to generate chip select signal
A. data
B. address
C. control bus
D. both (a) and (b)
Correct : B. address
62. _______ signal is generated by combining RD and WR signals with IO/M
A. control
B. memory
C. register
D. system
Correct : A. control
63. Memory is an integral part of a _______ system
A. supercomputer
B. microcomputer
C. mini computer
D. mainframe computer
Correct : B. microcomputer
64. _____ has certain signal requirements write into and read from its registers
A. memory
B. register
C. both (a) and (b)
D. control
Correct : A. memory
65. The memory chips such as 2732 EPROM and _________static R/W memory plays a major role in memory interfacing
A. 2732 EPROM
B. 6116
C. 8085
D. 8086
Correct : B. 6116
66. An _________ is used to fetch one address
A. internal decoder
B. external decoder
C. encoder
D. register
Correct : A. internal decoder
67. The primary function of the _____________ is to accept data from I/P devices
A. multiprocessor
B. microprocessor
C. peripherals
D. interfaces
Correct : B. microprocessor
68. Designing logic circuits and writing instructions to enable the microprocessor to communicate with peripheral is called _________
A. interfacing
B. monitoring
C. polling
D. pulling
Correct : A. interfacing
69. _______ means at the same time, the transmitter and receiver are synchronized with the same clock
A. asynchronous
B. serial data
C. synchronous
D. parallel data
Correct : C. synchronous
70. ________ means at irregular internals
A. asynchronous
B. synchronous
C. data transform
D. bus transform
Correct : A. asynchronous
71. ___________ signal prevent the microprocessor from reading the same data more than one
A. pipelining
B. handshaking
C. controlling
D. signaling
Correct : B. handshaking
72. Bits in IRR interrupt are ______
A. reset
B. set
C. stop
D. start
Correct : B. set
73. _________ decides the request of interrupt to be serviced
A. priority resolver
B. interrupt request register
C. interrupt mask register
D. control logic
Correct : A. priority resolver
74. __________ generate interrupt signal to microprocessor and receive acknowledge
A. priority resolver
B. control logic
C. interrupt request register
D. interrupt register
Correct : B. control logic
75. The _______ pin is used to select direct command word
A. A0
B. D7-D6
C. A12
D. AD7-AD6
Correct : A. A0
76. The _______ is used to connect more microproces
A. peripheral device
B. cascade
C. i/o deviced
D. control unit
Correct : B. cascade
77. OCW1 is used to set and read _____
A. OCW
B. IMR
C. ICWH
D. EOI
Correct : B. IMR
78. CS connect the output of ______
A. encoder
B. decoder
C. slave program
D. buffer
Correct : B. decoder
79. The 8259-A is a _________
A. piority Interrupt Controller
B. priority Resolver
C. interrupt Request Registry
D. control Logic
Correct : A. piority Interrupt Controller
80. The 8259A is used to manage _______ hardware in the system
A. Single
B. Multiple
C. Double
D. none
Correct : B. Multiple
81. ______ is used to transfer data between microprocessor and I/o process
A. 8255A
B. 8279
C. 8254A
D. 8237A
Correct : A. 8255A
82. 8255A contains_________ ports each of 8 bit lines
A. 2
B. 4
C. 5
D. 3
Correct : D. 3
83. In 8255A the ____ is controlled by control registers
A. port A
B. port B
C. port C
D. port D
Correct : C. port C
84. The read and write operation is done using ______
A. Iow/Ior
B. Iw/Ir
C. Iow
D. Ior
Correct : A. Iow/Ior
85. _______ is used to transfer address connect to address block
A. data bus
B. address bus
C. bus
D. flag
Correct : B. address bus
86. _________ performs the address decode operation
A. chip select
B. address bus
C. data bus
D. flag
Correct : A. chip select
87. In 8255A __________ is used for input operation
A. mode 0
B. mode2
C. mode 3
D. mode1
Correct : A. mode 0
88. In 8255A _________ is used for handshaking operation
A. mode 0
B. mode1
C. mode 2
D. mode3
Correct : B. mode1
89. In 8255 A ___________ is used to perform bidirectional operation
A. mode 0
B. mode1
C. mode 2
D. mode3
Correct : C. mode 2
90. Data transfer between the microprocessor for peripheral takes place through __________
A. i/o port
B. input port
C. output port
D. multi port
Correct : A. i/o port
91. The device such as buffer and batches are used as ____________
A. input port
B. output port
C. i/o port
D. multi port
Correct : C. i/o port
92. In 8255A, there are _________ I/o lines
A. 24
B. 12
C. 20
D. 10
Correct : A. 24
93. Port A and Port B are used individually as _______ I/o ports
A. 8
B. 16
C. 32
D. 4
Correct : A. 8
94. The 8255A is available with ________
A. 20
B. 40
C. 30
D. 10
Correct : B. 40
95. 8255A operates with ________ power supply
A. +5V
B. -5V
C. -10V
D. +10v
Correct : A. +5V
96. The pins are _______ data lines and are connected to data bus in system
A. unidirectional
B. bidirectional
C. directional
D. multidirectional
Correct : B. bidirectional
97. ________ are transferred on the data lines between microprocessor and internal port or control register
A. data, control and status bites
B. data and status bits
C. control and status bites
D. status bits
Correct : A. data, control and status bites
98. There are ________ address bus in 8255A
A. 2
B. 3
C. 4
D. 5
Correct : A. 2
99. The address bus enables the ________ for data transfer.
A. control register
B. data bus
C. address bus
D. both (b) and (c)
Correct : A. control register
100. The _____ are connected to 2 address bus line in system
A. address bus
B. data bus
C. Pins
D. control bus
Correct : C. Pins