Quiznetik
Digital Electronics | Set 5
1. For programmable logic functions, which type of PLD should be used?
A. pla
B. pal
C. cpld
D. sld
Correct : B. pal
2. The complex programmable logic device contains several PLD blocks and
A. a language compiler
B. and/or arrays
C. global interconnection matrix
D. field-programmable switches
Correct : C. global interconnection matrix
3. Which type of device FPGA are?
A. sld
B. srom
C. eprom
D. pld
Correct : D. pld
4. The difference between a PAL & a PLA is
A. pals and plas are the same thing
B. the pla has a programmable or plane and a programmable and plane, while the pal only has a programmable and plane
C. the pal has a programmable or plane and a programmable and plane, while the pla only has a programmable and plane
D. the pal has more possible product terms than the pla
Correct : B. the pla has a programmable or plane and a programmable and plane, while the pal only has a programmable and plane
5. If a PAL has been programmed once
A. its logic capacity is lost
B. its outputs are only active high
C. its outputs are only active low
D. it cannot be reprogrammed
Correct : D. it cannot be reprogrammed
6. The FPGA refers to
A. first programmable gate array
B. field programmable gate array
C. first program gate array
D. field program gate array
Correct : B. field programmable gate array
7. The full form of VLSI is
A. very long single integration
B. very least scale integration
C. very large scale integration
D. very long scale integration
Correct : C. very large scale integration
8. In FPGA, vertical and horizontal directions are separated by
A. a line
B. a channel
C. a strobe
D. a flip-flop
Correct : B. a channel
9. Applications of PLAs are
A. registered pals
B. configurable pals
C. pal programming
D. all of the mentioned
Correct : D. all of the mentioned
10. CMOS refers to
A. continuous metal oxide semiconductor
B. complementary metal oxide semiconductor
C. centred metal oxide semiconductor
D. concrete metal oxide semiconductor
Correct : B. complementary metal oxide semiconductor
11. Propagation delay is defined as
A. the time taken for the output of a gate to change after the inputs have changed
B. the time taken for the input of a gate to change after the outputs have changed
C. the time taken for the input of a gate to change after the intermediates have changed
D. the time taken for the output of a gate to change after the intermediates have changed
Correct : A. the time taken for the output of a gate to change after the inputs have changed
12. Propagation delay times can be divided as
A. t(plh) and t(lph)
B. t(lph) and t(phl)
C. t(plh) and t(phl)
D. t(hpl) and t(lph)
Correct : C. t(plh) and t(phl)
13. Power Dissipation in DIC is expressed in
A. watts or kilowatts
B. milliwatts or nanowatts
C. db
D. mdb
Correct : B. milliwatts or nanowatts
14. Fan-in is defined as
A. the number of outputs connected to gate without any degradation in the voltage levels
B. the number of inputs connected to gate without any degradation in the voltage levels
C. the number of outputs connected to gate with degradation in the voltage levels
D. the number of inputs connected to gate with degradation in the voltage levels
Correct : B. the number of inputs connected to gate without any degradation in the voltage levels
15. The maximum noise voltage that may appear at the input of a logic gate without changing the logical state of its output is termed as
A. noise margin
B. noise immunity
C. white noise
D. signal to noise ratio
Correct : B. noise immunity
16. The full form of ECL is
A. emitter-collector logic
B. emitter-complementary logic
C. emitter-coupled logic
D. emitter-cored logic
Correct : C. emitter-coupled logic
17. Which logic is the fastest of all the logic families?
A. ttl
B. ecl
C. htl
D. dtl
Correct : B. ecl
18. The full form of CML is
A. complementary mode logic
B. current mode logic
C. collector mode logic
D. collector mixed logic
Correct : C. collector mode logic
19. In an ECL the output is taken from
A. emitter
B. base
C. collector
D. junction of emitter and base
Correct : C. collector
20. The ECL behaves as
A. not gate
B. nor gate
C. nand gate
D. and gate
Correct : B. nor gate
21. In ECL the fanout capability is
A. high
B. low
C. zero
D. sometimes high and sometimes low
Correct : A. high
22. ECL’s major disadvantage is that
A. it requires more power
B. it’s fanout capability is high
C. it creates more noise
D. it is slow
Correct : A. it requires more power
23. The full form of SCFL is
A. source-collector logic
B. source-coupled logic
C. source-complementary logic
D. source cored logic
Correct : B. source-coupled logic
24. The equivalent of emitter-coupled logic made out of FETs is called
A. cml
B. scfl
C. fecl
D. efcl
Correct : B. scfl
25. ECL was invented in by
A. 1956, baker clamp
B. 1976, james r. biard
C. 1956, hannon s. yourke
D. 1976, yourke
Correct : C. 1956, hannon s. yourke
26. At the time of invention, an ECL was called as
A. source-coupled logic
B. current mode logic
C. current-steering logic
D. emitter-coupled logic
Correct : C. current-steering logic
27. The ECL circuits usually operates with
A. negative voltage
B. positive voltage
C. grounded voltage
D. high voltage
Correct : A. negative voltage
28. Low-voltage positive emitter-coupled logic (LVPECL) is a power optimized version of
A. ecl
B. vecl
C. pecl
D. lecl
Correct : C. pecl