1. How many select lines are required for a 1- to-8 demultiplexer?
Correct : B. 3
2. How many AND gates are required for a 1- to-8 multiplexer?
Correct : C. 8
3. Which IC is used for the implementation of 1-to-16 DEMUX?
Correct : A. ic 74154
4. All the comparisons made by comparator is done using
Correct : A. 1 circuit
5. One that is not the outcome of magnitude comparator is
Correct : B. a – b
6. If two numbers are not equal then binary variable will be
Correct : A. 0
7. How many inputs are required for a digital comparator?
Correct : A. 1
8. In a comparator, if we get input as A>B then the output will be
Correct : A. 1
9. Comparators are used in
Correct : B. cpu
10. A circuit that compares two numbers and determine their magnitude is called
Correct : D. magnitude comparator
11. A procedure that specifies finite set of steps is called
Correct : A. algorithm
12. How many types of digital comparators are?
Correct : B. 2
13. An identify comparator is defined as a digital comparator which has
Correct : A. only one output terminal
14. A magnitude comparator is defined as a digital comparator which has
Correct : C. three output terminals
15. The purpose of a Digital Comparator is
Correct : D. to compare a set of variables or unknown numbers
16. TTL 74LS85 is a
Correct : B. 4-bit magnitude comparator
17. 4 to 1 MUX would have
Correct : C. 4 inputs
18. A combinational circuit that selects one from many inputs are
Correct : D. multiplexer
19. 4 to 1 MUX would have
Correct : A. 1 output
20. Which of the following circuit can be used as parallel to serial converter?
Correct : A. multiplexer
21. The inputs/outputs of an analog multiplexer/demultiplexer are
Correct : A. bidirectional
22. If enable input is high then the multiplexer is
Correct : B. disable
23. What is data routing in a multiplexer?
Correct : D. both it can be used to route data and it is an application of multiplexer
24. How many inputs will a decimal-to-BCD encoder have?
Correct : C. 10
25. How many outputs will a decimal-to-BCD encoder have?
Correct : A. 4
26. How is an encoder different from a decoder?
Correct : A. the output of an encoder is a binary code for 1-of-n input
27. If we record any music in any recorder, such types of process is called
Correct : B. encoding
28. Can an encoder be a transducer?
Correct : A. yes
29. How many OR gates are required for a Decimal-to-bcd encoder?
Correct : D. 4
30. How many OR gates are required for an octal-to-binary encoder?
Correct : A. 3
31. Can an encoder be called as multiplexer?
Correct : B. yes
32. If two inputs are active on a priority encoder, which will be coded on the output?
Correct : A. the higher value
33. Latches constructed with NOR and NAND gates tend to remain in the latched condition due to which configuration feature?
Correct : D. cross coupling
34. One example of the use of an S-R flip-flop is as
Correct : C. switch debouncer
35. The truth table for an S-R flip-flop has how many VALID entries?
Correct : C. 3
36. When both inputs of a J-K flip-flop cycle, the output will
Correct : C. not change
37. Which of the following is correct for a gated D-type flip-flop?
Correct : A. the q output is either set or reset as soon as the d input goes high or low
38. A basic S-R flip-flop can be constructed by cross-coupling of which basic logic gates?
Correct : C. nor or nand gates
39. The logic circuits whose outputs at any instant of time depends only on the present input but also on the past outputs are called
Correct : B. sequential circuits
40. Whose operations are more faster among the following?
Correct : A. combinational circuits
41. How many types of sequential circuits are?
Correct : A. 2
42. The sequential circuit is also called
Correct : B. latch
43. The basic latch consists of
Correct : A. two inverters
44. In S-R flip-flop, if Q = 0 the output is said to be
Correct : B. reset
45. The output of latches will remain in set/reset untill
Correct : A. the trigger pulse is given to change the state
46. What is a trigger pulse?
Correct : A. a pulse that starts a cycle of operation
47. The circuits of NOR based S-R latch classified as asynchronous sequential circuits, why?
Correct : C. because of cross-coupled connection
48. Which are easier to design?
Correct : A. clocked circuits
49. is used to drive high capacitance load.
Correct : B. bipolar capability
50. As the temperature is increased, storage time
Correct : A. halved
51. Non inverting dynamic register storage cell consists of transistors for nMOS and for CMOS.
Correct : A. six, eight
52. Register cell consists of
Correct : C. inverter & pass transistor
53. In a four bit dynamic shift register basic nMOS transistor or inverters are connected in
Correct : B. cascade
54. In four bit dynamic shift register output is obtained
Correct : D. parallel output at inverter 2, 4, 6, 8
55. Output values of Moore type FSM are determined by its
Correct : D. current state
56. Moore machine output is synchronous.
Correct : A. true
57. Finite state machines are combinational logic systems.
Correct : B. false
58. What happens if the input is high in FSM?
Correct : A. change of state
59. What happens if the input is low in FSM?
Correct : B. no transition in state
60. In FSM diagram what does circle represent?
Correct : B. state
61. In the FSM diagram, what does arrow between the circles represent?
Correct : A. change of state
62. In the FSM diagram, what does the information below the line in the circle represent?
Correct : C. output value
63. Moore machine has states than a mealy machine.
Correct : B. more
64. State transition happens in every clock cycle.
Correct : A. once
65. In digital logic, a counter is a device which
Correct : B. stores the number of times a particular event or process has occurred
66. A counter circuit is usually constructed of
Correct : C. a number of flip-flops connected in cascade
67. A decimal counter has states.
Correct : B. 10
68. What is the maximum possible range of bit-count specifically in n-bit binary counter consisting of ‘n’ number of flip-flops?
Correct : C. 0 to 2n – 1
69. How many types of the counter are there?
Correct : B. 3
70. Three decade counter would have
Correct : B. 3 bcd counters
71. BCD counter is also known as
Correct : B. decade counter
72. The parallel outputs of a counter circuit represent the
Correct : D. clock count
73. Ring shift and Johnson counters are
Correct : A. synchronous counters
74. What is the difference between a shift-right register and a shift-left register?
Correct : B. the direction of the shift
75. What is a transceiver circuit?
Correct : C. a buffer that can operate in both directions
76. A 74HC195 4-bit parallel access shift register can be used for
Correct : D. all of the mentioned
77. What is the function of a buffer circuit?
Correct : B. to provide an output that is equal to its input
78. What is the preset condition for a ring shift counter?
Correct : D. a single 1, the rest 0
79. Another way to connect devices to a shared data bus is to use a
Correct : B. transceiver
80. The full form of SIPO is
Correct : A. serial-in parallel-out
81. A shift register that will accept a parallel input or a bidirectional serial load and internal shift features is called as?
Correct : C. universal
82. How can parallel data be taken out of a shift register simultaneously?
Correct : D. use the q output of each ff
83. What is meant by parallel load of a shift register?
Correct : A. all ffs are preset with data
84. The group of bits 11001 is serially shifted (right-most bit first) into a 5-bit parallel output shift register with an initial state 01110. After three clock pulses, the register contains
Correct : C. 00101
85. Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100. What will be the 4-bit pattern after the second clock pulse? (Right-most bit first)
Correct : C. 0000
86. A serial in/parallel out, 4-bit shift register initially contains all 1s. The data nibble 0111 is waiting to enter. After four clock pulses, the register contains
Correct : C. 0111
87. With a 200 kHz clock frequency, eight bits can be serially entered into a shift register in
Correct : B. 40 μs
88. An 8-bit serial in/serial out shift register is used with a clock frequency of 2 MHz to achieve a time delay (td) of
Correct : C. 4 us
89. A sequence of equally spaced timing pulses may be easily generated by which type of counter circuit?
Correct : A. ring shift
90. A bidirectional 4-bit shift register is storing the nibble 1101. Its input is HIGH. The nibble 1011 is waiting to be entered on the serial data-input line. After three clock pulses, the shift register is storing
Correct : B. 0111
91. How many clock pulses will be required to completely load serially a 5-bit shift register?
Correct : D. 5
92. How is an strobe signal used when serially loading a shift register?
Correct : B. to control the number of clocks
93. An 8-bit serial in/serial out shift register is used with a clock frequency of 150 kHz. What is the time delay between the serial input and the Q3 output?
Correct : B. 26.67 s
94. What are the three output conditions of a three-state buffer?
Correct : A. high, low, float
95. The primary purpose of a three-state buffer is usually
Correct : A. to provide isolation between the input device and the data bus
96. What is the difference between a ring shift counter and a Johnson shift counter?